1. Field of the Invention
This invention relates to surface mount chip packages such as chip size packages (or chip scale packages, i.e., CSPs), in which semiconductor chips are subjected to probing tests at precise positioning established with testers.
This application claims priority on Japanese Patent Application No. 2002-370205, the content of which is incorporated herein by reference.
2. Description of the Related Art
Chip size packages are known as one type of surface mount chip packages for holding semiconductor chips at prescribed positions; their sizes are substantially identical to sizes of semiconductor chips, so that they have been widely noted as packaging technologies realizing comprehensive reductions in scale and weight of electronic devices. When a semiconductor chip is mounted on a chip size package, a probing test is performed after a dicing process in order to increase the defect detection rate in a manufacturing stage. The probing test is performed on a wafer on which surface mold resins (or molded resins) as package housings are formed in advance and which is equipped with solder balls as external electrodes and is divided into pieces (or sections) by dicing, whereas an adhesive film is adhered to the backside of the wafer so as to maintain the original shape of the wafer even though the dicing is performed. The probing test is performed on each of individual sections of the wafer. In the following description, each individual section of the wafer, on which surface mold resins are formed and which is divided by dicing, is called a device chip, which is distinguished from a bare chip corresponding to the semiconductor chip in terminology.
The probing test is performed by bringing a probe electrode of a tester therefor into contact with electrodes of the device chip; therefore, it is necessary to establish prescribed positioning between the probe electrode and the electrodes of the device chip. In the general probing test that is performed on the other type of a package (without using a chip size package), prescribed positioning is established upon recognition of the inclination (or a rotation angle θ) and position (X-Y coordinates) of a wafer based on a specific pattern of wires and scribe lines formed on a semiconductor chip, an example of which is disclosed in Japanese Patent Application Publication No. Hei 3-142848. In contrast, the chip size package is designed such that the semiconductor chip is covered with a mold resin, and it does not allow recognition of a specific pattern formed on the semiconductor chip when viewed from the exterior thereof. For this reason, in the probing test using the chip size package, the prescribed positioning is established upon recognition of an arrangement of plural solder balls as external electrodes.
FIG. 6 shows an example of an arrangement of solder balls 510 that are arranged on the surface (or the backside) of a package housing 500 (i.e., a mold resin) of the conventional chip size package. Herein, solder balls 510 are arranged in a matrix on the entire surface of the package housing 500, except at its center area, in such a way that eight balls are arranged in an X-axis direction, and six balls are arranged in a Y-axis direction. In addition, there is provided an index solder ball 520 for use in the user's recognition of a chip direction. In the probing test, an image of the plural solder balls 510 existing in a prescribed range of area is picked up and is subjected to image processing, thus determining a straight line Lx connecting the centers (or outer circumferences) of the balls lying in the X-axis direction and a straight line Ly connecting the centers (or outer circumferences) of the balls lying in the Y-axis direction. In order to set the reference for the positioning in the X-Y plane, a reference axis AX is set in the X-axis direction, and a reference axis AY is set in the Y-axis direction. That is, the prescribed positioning is established upon determination of the inclination of the device chip based on an angle θx formed between the reference axis AX and the straight line Lx, and an angle θy formed between the reference axis AY and the straight line Ly.
In the conventional technology for the detection of solder balls described above, it is necessary to use a special image processing technique in consideration of deformations of individual solder balls in order to determine the straight lines Lx and Ly each connecting solder balls. In other words, it is very difficult to use the existing image processing technique for the recognition of a specific pattern on the semiconductor chip. Because of the necessity of determining straight lines each connecting solder balls, it is necessary to pick up an image of solder balls existing in a relatively broad area. For this reason, it is very difficult to use the conventional image pickup device that can merely pick up a pattern with respect to a specific small area. This may raise the necessity for the user to repeatedly change the image pickup area covered by the image pickup device.
Each of the solder balls has an approximately circular shape; therefore, it is very difficult to recognize the inclination of the semiconductor chip upon detection of a single solder ball. For this reason, solder balls may be difficult to use for the detection of the aforementioned specific pattern, and it is therefore very difficult to use existing image processing techniques.
As a result, in the probing test using the chip size package, it is necessary to determine the arrangement of solder balls existing over a relatively broad area. This requires troublesome work to prepare a special image processing program and a special image pickup device for the probing test.